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enjoy-digital/litex

Python framework for building custom FPGA cores and SoCs, with buses, peripherals, CPU integration and simulation support.

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What is it?

LiteX is a Python-based SoC builder for FPGAs. It provides the common building blocks needed to assemble a full system on an FPGA: bus and stream interconnects (Wishbone, AXI, Avalon-ST), simple cores such as RAM, ROM, timers, UART and JTAG, and bridges for host-side debugging of a running SoC.

The framework is built on Migen and connects to a wider ecosystem of separate cores, including LiteDRAM, LitePCIe, LiteEth and LiteSATA. It supports several soft CPUs such as VexRiscv, Rocket, LM32 and PicoRV32, and can be combined with existing VHDL, Verilog or SystemVerilog code. Designs can be built for vendor FPGA toolchains or simulated with Verilator without hardware.

LiteX suits hardware engineers who want to reuse IP cores in a scripted flow, and software developers who want to start working with FPGAs through Python.

Key features

  • 01Wishbone, AXI and Avalon-ST bus and stream interconnects.
  • 02Ready-made cores including RAM, ROM, timer, UART and JTAG.
  • 03Support for multiple soft CPUs such as VexRiscv, Rocket and PicoRV32.
  • 04Mixed-language integration with VHDL, Verilog and SystemVerilog.
  • 05Verilator-based simulation of SoCs without an FPGA board.
  • 06Build backends for open-source and vendor FPGA toolchains.

Use cases

  • Assembling a custom FPGA SoC with a soft CPU and peripherals.
  • Reusing existing PCIe, Ethernet or SATA cores inside a traditional HDL flow.
  • Simulating a full SoC on a desktop before running it on hardware.
  • Learning FPGA design through a Python-based workflow.

Quick start

  1. 1

    Install Python 3.7+ and FPGA vendor tools and/or Verilator

  2. 2

    Download the litex_setup.py script

    wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
  3. 3

    Make the script executable

    chmod +x litex_setup.py
  4. 4

    Install Migen, LiteX and the standard set of cores

    ./litex_setup.py --init --install --user --config=standard

Things to know

  • Building real FPGA bitstreams requires separately installed vendor toolchains or Verilator.
  • Digital logic is described with Migen, which the project itself notes is the current base.

In collections

Robotics & embodied AI projects

Topics

#fpga#hardware#soc#python#risc-v#verilog#simulation#system-on-chip

FAQ

What is litex?
Python framework for building custom FPGA cores and SoCs, with buses, peripherals, CPU integration and simulation support. LiteX is a Python-based SoC builder for FPGAs. It provides the common building blocks needed to assemble a full system on an FPGA: bus and stream interconnects (Wishbone, AXI, Avalon-ST), simple cores such as RAM, ROM, timers, UART and JTAG, and bridges for host-side debugging of a running SoC.
Is litex free to use? What license does it have?
litex is open source under the Other license. Check the license terms before using it in commercial products.
Is litex still maintained?
Actively maintained. The last commit to litex was on Nov 6, 2026.
What can I use litex for?
Assembling a custom FPGA SoC with a soft CPU and peripherals. Reusing existing PCIe, Ethernet or SATA cores inside a traditional HDL flow. Simulating a full SoC on a desktop before running it on hardware. Learning FPGA design through a Python-based workflow.
How do I install litex?
Install Python 3.7+ and FPGA vendor tools and/or Verilator Download the litex_setup.py script: wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py Make the script executable: chmod +x litex_setup.py Install Migen, LiteX and the standard set of cores: ./litex_setup.py --init --install --user --config=standard
Where can I get litex?
The source code and installation instructions are on GitHub: https://github.com/enjoy-digital/litex

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