#rtl
Best open-source RTL hardware designs and UI templates (2026)
This page covers two groups that share the RTL label: register-transfer-level hardware and right-to-left UI templates. For hardware, check the language and target: Chisel generates Verilog from Scala, while ibex is a small 32-bit RISC-V core in SystemVerilog for embedded control. For admin UIs, check the framework and whether you need RTL layouts; Tabler is a Bootstrap 5 kit with dark mode, and shadcn-admin is built on Shadcn UI and Vite.
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A 64-bit RISC-V CPU core written in SystemVerilog that boots Linux on an Arty A7 FPGA board, with the RTL, verification and documents all written by Claude Code.
An admin dashboard UI template built with Shadcn UI components and Vite, with light/dark mode, RTL support, and a global search command.
An open-source hardware description language embedded in Scala for writing parameterizable digital circuit generators that emit Verilog.
Free, open source Bootstrap 5 HTML dashboard UI kit with ready-made admin pages, components, dark mode and RTL support.