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OpenXiangShan

OpenXiangShan/XiangShan

Open-source high-performance RISC-V processor core written in Scala with Chisel, developed by the XiangShan project.

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What is it?

XiangShan is an open-source high-performance RISC-V processor project. The design is written in Chisel, a hardware construction language embedded in Scala, and it generates Verilog that can be used for chip development.

The repository holds successive microarchitecture generations, including Yanqihu, Nanhu and Kunminghu, each kept on its own branch. Kunminghu-V2 and V3 are the current lines, with V3 under active development. The project also covers the surrounding toolchain: a Verilator-based C++ emulator, a difftest co-simulation framework, a cache subsystem and a Python-based debugger (xspdb).

A design document and user guide are published separately on the project's documentation site, and a performance dashboard tracks commit-level and SPEC regression results.

Key features

  • 01Implements the RISC-V instruction set in a high-performance out-of-order microarchitecture.
  • 02Written in Chisel and generates Verilog via make verilog.
  • 03Includes a Verilator-based C++ simulator that runs RISC-V binaries.
  • 04Provides difftest co-simulation against the NEMU reference model.
  • 05Offers a Python-based debugger, xspdb, for stepping and inspecting execution.

Use cases

  • Researching processor microarchitecture with a full-featured open RISC-V core.
  • Studying hardware verification and co-simulation workflows.
  • Building downstream RISC-V chip designs based on the released Verilog.
  • Benchmarking RISC-V workloads in a Verilator simulator.

Quick start

  1. 1

    Set NEMU_HOME, NOOP_HOME and AM_HOME environment variables and install mill

  2. 2

    Clone the project and initialize submodules

    make init
  3. 3

    Install Verilator, then build the C++ simulator

    make emu CONFIG=MinimalConfig EMU_THREADS=2 -j10
  4. 4

    Run a program on the simulator

    ./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so

Things to know

  • Building requires several external projects (NEMU, nexus-am, mill, Verilator), so setup is heavy.
  • The kunminghu-v3 branch is still evolving and may not be stable; kunminghu-v2 is recommended for research.

Topics

#risc-v#processor#chisel#hardware#microarchitecture#verilog#cpu-design

FAQ

What is XiangShan?
Open-source high-performance RISC-V processor core written in Scala with Chisel, developed by the XiangShan project. XiangShan is an open-source high-performance RISC-V processor project. The design is written in Chisel, a hardware construction language embedded in Scala, and it generates Verilog that can be used for chip development.
Is XiangShan free to use? What license does it have?
XiangShan is open source under the MulanPSL-2.0 license. Check the license terms before using it in commercial products.
Is XiangShan still maintained?
Actively maintained. The last commit to XiangShan was on Nov 6, 2026.
What can I use XiangShan for?
Researching processor microarchitecture with a full-featured open RISC-V core. Studying hardware verification and co-simulation workflows. Building downstream RISC-V chip designs based on the released Verilog. Benchmarking RISC-V workloads in a Verilator simulator.
How do I install XiangShan?
Set NEMU_HOME, NOOP_HOME and AM_HOME environment variables and install mill Clone the project and initialize submodules: make init Install Verilator, then build the C++ simulator: make emu CONFIG=MinimalConfig EMU_THREADS=2 -j10 Run a program on the simulator: ./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so
Where can I get XiangShan?
The source code and installation instructions are on GitHub: https://github.com/OpenXiangShan/XiangShan

Summary generated by AI from the project's README. GitHub stats refresh daily.

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