chipsalliance/chisel

What is it?

Key features

• 01Describes hardware in Scala, reusing classes, functions and loops for parameterized circuits.
• 02Emits synthesizable Verilog or SystemVerilog through ChiselStage and firtool.
• 03Provides a standard library with FIFO queues, arbiters and Decoupled ready-valid interfaces.
• 04Includes svsim for running simulations on Verilator and VCS.
• 05Builds with Mill and publishes artifacts for use with sbt projects.

Use cases

• Writing reusable, parameterized IP blocks for ASIC or FPGA designs.
• Building processor or accelerator designs that need generator-style code.
• Learning digital design with a modern programming language and online tutorials.
• Generating Verilog from Scala code for downstream synthesis and simulation flows.

Quick start

1. 1

   Start from the Chisel Template repository, which provides a pre-configured project

2. 2

   Or set up your own project by adding the Chisel dependency and compiler plugin to build.sbt

3. 3

   Try the online Chisel Bootcamp tutorial in the browser, with no setup needed

Things to know

• !Requires a Scala and sbt toolchain on the JVM, which adds setup overhead.
• !Verilog generation depends on the firtool compiler, so some online playgrounds such as Scastie cannot emit Verilog.

Topics

FAQ

What is chisel?

An open-source hardware description language embedded in Scala for writing parameterizable digital circuit generators that emit Verilog. Chisel (Constructing Hardware in a Scala Embedded Language) is a hardware description language for designing digital electronics at the register-transfer level. Instead of writing Verilog by hand, designers write Scala code that builds circuits, so ordinary programming constructs like functions, classes, and loops can be used to generate hardware. The output is synthesizable Verilog or SystemVerilog, usable for both ASIC and FPGA designs.

Is chisel free to use? What license does it have?

chisel is open source under the Apache-2.0 license. Check the license terms before using it in commercial products.

Is chisel still maintained?

Actively maintained. The last commit to chisel was on Nov 6, 2026.

What can I use chisel for?

Writing reusable, parameterized IP blocks for ASIC or FPGA designs. Building processor or accelerator designs that need generator-style code. Learning digital design with a modern programming language and online tutorials. Generating Verilog from Scala code for downstream synthesis and simulation flows.

How do I install chisel?

Start from the Chisel Template repository, which provides a pre-configured project Or set up your own project by adding the Chisel dependency and compiler plugin to build.sbt Try the online Chisel Bootcamp tutorial in the browser, with no setup needed

Where can I get chisel?

The source code and installation instructions are on GitHub: https://github.com/chipsalliance/chisel