munetomo-maruyama/mmRISC-2
A 64-bit RISC-V CPU core written in SystemVerilog that boots Linux on an Arty A7 FPGA board, with the RTL, verification and documents all written by Claude Code.
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What is it?
mmRISC-2 is a home-made 64-bit RISC-V processor (RV64GC) written in SystemVerilog, targeting the Digilent Arty A7-100T FPGA board. It includes an 8-stage in-order pipeline, Sv39 MMU with PMP, branch prediction, a single and double precision FPU, 16 KB L1 instruction and data caches, and a 256 KB L2 cache. Peripherals come from LiteX, and on-chip JTAG/cJTAG debug is provided.
On the board at 50 MHz, the project boots LiteX BIOS, OpenSBI and Linux 7.2 from an SD card to a BusyBox shell, and Debian 13 (riscv64) can also boot, with gcc, make and gdb running on the board itself. Bare-metal C programs can be built and debugged in the Eclipse IDE over JTAG. The core exposes 29 performance counter events usable with Linux perf.
The repository also documents the verification environment, which includes home-made tests, riscv-tests, reference models and bug injection, along with the design history and specifications in both English and Japanese.
Key features
- 01RV64GC core with M, S and U modes, Sv39 MMU and 8-entry PMP.
- 028-stage in-order pipeline with branch prediction (BTB, gshare, return address stack).
- 03Single and double precision FPU with a pipelined datapath.
- 0416 KB L1 instruction and data caches plus a 256 KB L2 cache.
- 05Boots Linux 7.2 and Debian 13 from an SD card on the Arty A7-100T.
- 06JTAG/cJTAG on-chip debug with hardware triggers, usable with OpenOCD and gdb.
Use cases
- Studying how a RISC-V CPU core, caches and MMU are built in SystemVerilog.
- Running Linux on a custom RISC-V core on an inexpensive FPGA board.
- Bare-metal C development and debugging on an FPGA-hosted RISC-V core via Eclipse.
- Reference for processor verification with reference models and bug injection.
Things to know
- It runs on a specific FPGA board, the Digilent Arty A7-100T, so it cannot run on other hardware without porting.
- The project closes with Rev.02, so no further development is planned.
Topics
FAQ
- What is mmRISC-2?
- A 64-bit RISC-V CPU core written in SystemVerilog that boots Linux on an Arty A7 FPGA board, with the RTL, verification and documents all written by Claude Code. mmRISC-2 is a home-made 64-bit RISC-V processor (RV64GC) written in SystemVerilog, targeting the Digilent Arty A7-100T FPGA board. It includes an 8-stage in-order pipeline, Sv39 MMU with PMP, branch prediction, a single and double precision FPU, 16 KB L1 instruction and data caches, and a 256 KB L2 cache. Peripherals come from LiteX, and on-chip JTAG/cJTAG debug is provided.
- Is mmRISC-2 free to use? What license does it have?
- mmRISC-2 is open source under the Apache-2.0 license. Check the license terms before using it in commercial products.
- Is mmRISC-2 still maintained?
- Actively maintained. The last commit to mmRISC-2 was on Oct 20, 2026.
- What can I use mmRISC-2 for?
- Studying how a RISC-V CPU core, caches and MMU are built in SystemVerilog. Running Linux on a custom RISC-V core on an inexpensive FPGA board. Bare-metal C development and debugging on an FPGA-hosted RISC-V core via Eclipse. Reference for processor verification with reference models and bug injection.
- Where can I get mmRISC-2?
- The source code and installation instructions are on GitHub: https://github.com/munetomo-maruyama/mmRISC-2
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