A 64-bit RISC-V CPU core written in SystemVerilog that boots Linux on an Arty A7 FPGA board, with the RTL, verification and documents all written by Claude Code.
168+4 this week32SystemVerilogApache-2.0Updated 18 days ago
lowRISC/ibex
A small, production-quality 32-bit RISC-V CPU core written in SystemVerilog, aimed at embedded control applications.
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What is it?
Ibex is a 32-bit RISC-V CPU core written in SystemVerilog. It is heavily parametrizable, so designers can trade off performance, area and security features by choosing configuration options such as the multiplier architecture. It supports the I or E base integer set along with the M, C and B extensions, and also supports the CHERIoT 1.0 base ISA.
Ibex was originally developed as part of the PULP platform under the name Zero-riscy and is now maintained and developed further by lowRISC. The project publishes a set of supported configurations with CoreMark performance, Yosys and estimated commercial synthesis area, and verification maturity for each.
The repository includes the Simple System, a simulation-oriented integration for running bare metal binaries, along with a user manual hosted on ReadTheDocs. A more complete FPGA-based example is maintained separately in the Ibex Demo System repository.
Key features
- 01Supports RV32I or RV32E base integer ISA with M, C and B extensions.
- 02Heavily parametrizable, with multiple multiplier and performance/security options.
- 03Provides published CoreMark, area and verification status for several preset configurations.
- 04Includes a simulation-ready Simple System example for running bare metal binaries.
- 05Supports the CHERIoT 1.0 base ISA.
Use cases
- Building a small embedded microcontroller that needs a simple RISC-V control core.
- Evaluating RISC-V core area and performance trade-offs across configurations before tapeout.
- Running bare metal software on a RISC-V core in simulation.
- Studying or teaching a production-quality RISC-V core implementation in SystemVerilog.
Things to know
- Some configurations, such as the micro RV32EC config, have minimal verification, so users must assess verification readiness themselves before any tapeout.
- The README does not describe a simple install or run path; it is a hardware RTL core that is typically used through its simulation examples and documentation.
In collections
Topics
FAQ
- What is ibex?
- A small, production-quality 32-bit RISC-V CPU core written in SystemVerilog, aimed at embedded control applications. Ibex is a 32-bit RISC-V CPU core written in SystemVerilog. It is heavily parametrizable, so designers can trade off performance, area and security features by choosing configuration options such as the multiplier architecture. It supports the I or E base integer set along with the M, C and B extensions, and also supports the CHERIoT 1.0 base ISA.
- Is ibex free to use? What license does it have?
- ibex is open source under the Apache-2.0 license. Check the license terms before using it in commercial products.
- Is ibex still maintained?
- Actively maintained. The last commit to ibex was on Nov 6, 2026.
- What can I use ibex for?
- Building a small embedded microcontroller that needs a simple RISC-V control core. Evaluating RISC-V core area and performance trade-offs across configurations before tapeout. Running bare metal software on a RISC-V core in simulation. Studying or teaching a production-quality RISC-V core implementation in SystemVerilog.
- Where can I get ibex?
- The source code and installation instructions are on GitHub: https://github.com/lowRISC/ibex
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