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Best open-source SystemVerilog projects
Open-source projects written in SystemVerilog, ranked by stars with AI summaries and license info.
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A 64-bit RISC-V CPU core written in SystemVerilog that boots Linux on an Arty A7 FPGA board, with the RTL, verification and documents all written by Claude Code.
168+4 this week32SystemVerilogApache-2.0Updated 18 days ago