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cvut/qtrvsim

A Qt-based RISC-V CPU simulator for teaching computer architecture, with a WebAssembly build that runs in the browser.

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Last commit
9 days ago

What is it?

QtRvSim is a graphical RISC-V CPU simulator built for computer architecture courses. It loads statically linked 32-bit or 64-bit little-endian ELF executables and runs them, with the simulator selecting XLEN from the ELF header. It includes a basic integrated assembler and can call an external make utility to build the program being edited.

The simulator models a set of memory-mapped peripherals: a UART serial port, an LED and knob panel, an RGB565 LCD framebuffer, and ACLINT timer and software interrupt devices. It also implements a subset of CSRs and interrupt handling, plus a small set of Linux system calls such as read, write, openat and exit for running simple programs.

The project is developed by the Computer Architectures Education group at Czech Technical University. A WebAssembly version can be tried online without installation, though it is marked experimental. Binary packages are available for several Linux distributions, and it builds with Qt 5 or Qt 6 using CMake.

Key features

  • 01Runs statically linked RISC-V ELF executables in 32-bit and 64-bit modes.
  • 02Includes a basic integrated assembler that accepts a subset of GNU assembler directives.
  • 03Emulates UART, LED/knob panel, LCD framebuffer and ACLINT timer peripherals.
  • 04Implements common CSRs and interrupt handling for the machine mode.
  • 05Provides a set of Linux system calls for running simple programs.
  • 06Runs in the browser through a WebAssembly build.

Use cases

  • Teaching undergraduate or graduate computer architecture courses with a visual CPU model.
  • Demonstrating how serial I/O, interrupts and timers interact with a RISC-V program.
  • Testing small RISC-V assembly or C programs compiled with GCC or Clang before running on hardware.

Quick start

  1. 1

    Clone the repository with its submodules

    git clone --recurse-submodules https://github.com/cvut/qtrvsim.git
  2. 2

    Run make in the project root on Linux to build with the wrapper Makefile

    make
  3. 3

    Or try the experimental WebAssembly version in your browser without installing

Things to know

  • Licensed under GPL-3.0, a copyleft license that requires derivative works to be open-sourced under the same terms.
  • Compressed RISC-V instructions are not yet supported.
  • The WebAssembly version is experimental.

Topics

#risc-v#cpu-simulator#computer-architecture#teaching#emulator#webassembly#qt#cpu-emulator

FAQ

What is qtrvsim?
A Qt-based RISC-V CPU simulator for teaching computer architecture, with a WebAssembly build that runs in the browser. QtRvSim is a graphical RISC-V CPU simulator built for computer architecture courses. It loads statically linked 32-bit or 64-bit little-endian ELF executables and runs them, with the simulator selecting XLEN from the ELF header. It includes a basic integrated assembler and can call an external make utility to build the program being edited.
Is qtrvsim free to use? What license does it have?
qtrvsim is open source under the GPL-3.0 license. Check the license terms before using it in commercial products.
Is qtrvsim still maintained?
Actively maintained. The last commit to qtrvsim was on Oct 29, 2026.
What can I use qtrvsim for?
Teaching undergraduate or graduate computer architecture courses with a visual CPU model. Demonstrating how serial I/O, interrupts and timers interact with a RISC-V program. Testing small RISC-V assembly or C programs compiled with GCC or Clang before running on hardware.
How do I install qtrvsim?
Clone the repository with its submodules: git clone --recurse-submodules https://github.com/cvut/qtrvsim.git Run make in the project root on Linux to build with the wrapper Makefile: make Or try the experimental WebAssembly version in your browser without installing
Where can I get qtrvsim?
The source code and installation instructions are on GitHub: https://github.com/cvut/qtrvsim

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